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| GS1575A / GS9075A HD-LINX(R) II Multi-Rate SDI Automatic Reclocker GS1575A / GS9075A Data Sheet Features GS1575A * * * * * * * * * * * * * * * SMPTE 292M, 259M and 344M compliant Supports data rates of 143, 177, 270, 360, 540, 1483.5, 1485 Mb/s Supports DVB-ASI at 270Mb/s Pb-free and RoHS Compliant Auto and Manual Modes for rate selection Standards indication in Auto Mode 4:1 input multiplexer Loss of Signal (LOS) Output Lock Detect Output On-chip Input and Output Termination Differential 50 inputs and outputs Mute, Bypass and Autobypass functions SD/HD indication output to control GS1528A Dual Slew-Rate Cable Driver Single 3.3V power supply Operating temperature range: 0C to 70C Description The GS1575A/9075A is a Multi-Rate Serial Digital Reclocker designed to automatically recover the embedded clock from a digital video signal and re-time the incoming video data. The GS1575A Serial Digital Reclocker will recover the embedded clock signal and re-time the data from a SMPTE 292M, SMPTE 259M or SMPTE 344M compliant digital video signal. The GS9075A Serial Digital Reclocker will recover the embedded clock signal and re-time the data from a SMPTE 259M or SMPTE 344M compliant digital video signal. The GS1575A/9075A removes the high frequency jitter components from the bit-serial stream. Input termination is on-chip for seamless matching to 50 transmission lines. An LVPECL compliant output interfaces seamlessly to the GS1578A/GS9078A Cable Driver. The GS1575A/9075A can operate in either auto or manual rate selection mode. In Auto mode the device will automatically detect and lock onto incoming SMPTE SDI data signals at any supported rate. For single rate data systems, the GS1575A/9075A can be configured to operate in Manual mode. In both modes, the device requires only one external crystal to set the VCO frequency when not locked and provides adjustment free operation. In systems which require passing of non-SMPTE data rates, the GS1575A/9075A can be configured to either automatically or manually enter a bypass mode in order to pass the signal without reclocking. The ASI/177 input pin allows for manual selection of support of either 177Mb/s or DVB-ASI inputs. The GS1575A/9075A is Pb-free, and the encapsulation compound does not contain halogenated flame retardant. This component and all homogeneous sub-components are RoHS compliant. GS9075A * * * * * * * * * * * * * * SMPTE 259M and 344M compliant Supports data rates of 143, 177, 270, 360, and 540Mb/s Supports DVB-ASI at 270Mb/s Pb-free and RoHS Compliant Auto and Manual Modes for rate selection Standards indication in Auto Mode 4:1 input multiplexer Loss of Signal (LOS) Output Lock Detect Output On-chip Input and Output Termination Differential 50 inputs and outputs Mute, Bypass and Autobypass functions Single 3.3V power supply Operating temperature range: 0C to 70C Applications GS1575A * SMPTE 292M, SMPTE 259M and SMPTE 344M Serial Digital Interfaces GS9075A * SMPTE 259M and SMPTE 344M Serial Digital Interfaces. 34716 - 0 December 2005 1 of 29 www.gennum.com GS1575A / GS9075A Data Sheet XTAL+ XTAL- XTAL XTAL OUT+ OUT- LF+ LF- KBB XTAL OSC BUFFER RE-TIMER M U X DATA BUFFER DDO/DDO DDO_MUTE SCO_ENABLE DDI 0 PHASE FREQUENCY DETECTOR D A T A M U X M U X CHARGE PUMP CLOCK BUFFER SCO/SCO VCO DDI 1 PHASE DETECTOR DIVIDE BY 2,4,6,8,12,16 DIVIDE BY 152, 160, 208 DDI 2 DDI 3 DDI_SEL[1:0] CONTROL LOGIC BYPASS LOGIC SS[2:0] ASI/177 AUTO/MAN SD/HD LD LOS AUTOBYPASS BYPASS GS1575A Functional Block Diagram XTAL+ XTAL- XTAL XTAL OUT+ OUT- LF+ LF- KBB XTAL OSC BUFFER RE-TIMER M U X DATA BUFFER DDO/DDO DDO_MUTE SCO_ENABLE DDI 0 PHASE FREQUENCY DETECTOR D A T A M U X M U X CHARGE PUMP CLOCK BUFFER SCO/SCO VCO DDI 1 PHASE DETECTOR DIVIDE BY 2,4,6,8,12 DIVIDE BY 152, 160 DDI 2 DDI 3 DDI_SEL[1:0] CONTROL LOGIC BYPASS LOGIC SS[2:0] ASI/177 AUTO/MAN SD/HD LD LOS AUTOBYPASS BYPASS GS9075A Functional Block Diagram 34716 - 0 December 2005 2 of 29 GS1575A / GS9075A Data Sheet Contents Features ........................................................................................................................1 Applications...................................................................................................................1 Description ....................................................................................................................1 1. Pin Out ......................................................................................................................4 1.1 GS1575A Pin Assignment ..............................................................................4 1.2 GS9075A Pin Assignment ..............................................................................5 1.3 Pin Descriptions ..............................................................................................6 2. Electrical Characteristics ...........................................................................................9 2.1 Absolute Maximum Ratings ............................................................................9 2.2 DC Electrical Characteristics ..........................................................................9 2.3 AC Electrical Characteristics .........................................................................10 2.4 Solder Reflow Profiles ...................................................................................13 3. Input / Output Circuits .............................................................................................14 4. Detailed Description ................................................................................................17 4.1 Slew Rate Phase Lock Loop (S-PLL) ...........................................................17 4.2 VCO ..............................................................................................................18 4.3 Charge Pump ................................................................................................18 4.4 Frequency Acquisition Loop -- The Phase-Frequency Detector ..................19 4.5 Phase Acquisition Loop -- The Phase Detector ...........................................19 4.6 4:1 Input Mux ................................................................................................20 4.7 Automatic and Manual Data Rate Selection .................................................20 4.8 Bypass Mode ................................................................................................21 4.9 DVB-ASI Operation .......................................................................................21 4.10 Lock and LOS .............................................................................................22 4.11 Output Drivers and Serial Clock Outputs ....................................................22 4.12 Output Mute ................................................................................................23 5. Typical Application Circuits .....................................................................................24 6. Package & Ordering Information .............................................................................26 6.1 Package Dimensions ....................................................................................26 6.2 Recommended PCB Footprint ......................................................................27 6.3 Packaging Data .............................................................................................28 6.4 Ordering Information .....................................................................................28 7. Revision History ......................................................................................................29 34716 - 0 December 2005 3 of 29 GS1575A / GS9075A Data Sheet 1. Pin Out 1.1 GS1575A Pin Assignment XTAL_OUTXTAL_OUT+ VCC_CP VEE_CP XTAL+ XTAL- GND LF- DDI0 DDI0_VTT DDI0 GND DDI1 DDI1_VTT DDI1 GND DDI2 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 GND LF+ NC NC NC NC NC NC VEE_DDO VCC_DDO DDO NC DDO GND_DRV VEE_SCO VCC_SCO SCO - 2 3 4 5 6 7 8 9 10 11 12 13 14 - GS1575A 64-pin QFN (Top View) 42 41 40 39 38 37 36 35 DDI2_VTT - DDI2 GND DDI3 DDI3_VTT DDI3 GND - SCO GND DDO_MUTE SCO_ENABLE KBB SD/HD NC - 34 15 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DDI_SEL1 BYPASS AUTOBYPASS VCC_VCO VEE_VCO LOCKED LOS VCC_DIG SS0 SS1 SS2 DDI_SEL0 VEE_DIG ASI/177 Ground Pad (bottom of package) Figure 1-1: 64-Pin QFN 34716 - 0 December 2005 AUTO/MAN GND 4 of 29 GS1575A / GS9075A Data Sheet 1.2 GS9075A Pin Assignment XTAL_OUTXTAL_OUT+ VCC_CP VEE_CP XTAL+ XTAL- GND LF- DDI0 DDI0_VTT DDI0 GND DDI1 DDI1_VTT DDI1 GND DDI2 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 GND LF+ NC NC NC NC NC NC VEE_DDO VCC_DDO DDO NC DDO GND_DRV VEE_SCO VCC_SCO SCO - 2 3 4 5 6 7 8 9 10 11 12 13 14 - GS9075A 64-pin QFN (Top View) 42 41 40 39 38 37 36 35 DDI2_VTT - DDI2 GND DDI3 DDI3_VTT DDI3 GND - SCO GND DDO_MUTE SCO_ENABLE KBB SD NC - 34 15 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VEE_VCO LOCKED LOS VCC_DIG DDI_SEL1 BYPASS AUTOBYPASS VCC_VCO VEE_DIG SS0 SS1 SS2 DDI_SEL0 Ground Pad (bottom of package) Figure 1-2: 64-Pin QFN 34716 - 0 December 2005 AUTO/MAN ASI/177 GND 5 of 29 GS1575A / GS9075A Data Sheet 1.3 Pin Descriptions Table 1-1: Pin Descriptions Pin Number 1, 3 2 4, 8, 12,16, 32, 37, 43, 49, 64 5, 7 6 9, 11 10 13, 15 14 17, 18 Name DDI0, DDI0 DDI0_VTT GND DDI1,DDI1 DDI1_VTT DDI2, DDI2 DDI2_VTT DDI3, DDI3 DDI3_VTT DDI_SEL[1:0] Type Input Passive Passive Input Passive Input Passive Input Passive Logic Input Description Serial digital differential input 0. Center tap of two 50 on-chip termination resistors between DDI0 and DDI0. Recommended connect to GND. Serial digital differential input 1. Center tap of two 50 on-chip termination resistors between DDI1 and DDI1. Serial digital differential input 2. Center tap of two 50 on-chip termination resistors between DDI2 and DDI2. Serial digital differential input 3. Center tap of two 50 on-chip termination resistors between DDI3 and DDI3. Serial digital input select. DDI_SEL1 0 0 1 1 DDI_SEL0 0 1 0 1 INPUT SELECTED DDI0 DDI1 DDI2 DDI3 19 BYPASS Logic Input Bypass the reclocker stage. When BYPASS is HIGH, it overwrites the AUTOBYPASS setting. 20 AUTOBYPASS Logic Input Automatically bypasses the reclocker stage when the PLL is not locked This pin is ignored when BYPASS is HIGH. 21 AUTO/MAN Logic Input Auto/Manual select. When set HIGH, the standard is automatically detected from the input data rate. When set LOW, the user must program the input standard using the SS[2:0] pins. 22 VCC_VCO Power Most positive power supply connection for the internal VCO section. Connect to 3.3V. 23 VEE_VCO Power Most negative power supply connection for the internal VCO section. Connect to GND. 34716 - 0 December 2005 6 of 29 GS1575A / GS9075A Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 24, 25, 26 Name SS[2:0] Type Bi-directional Description When AUTO/MAN is HIGH, SS[0:2] are outputs, displaying the data rate to which the PLL has locked. When AUTO/MAN is LOW, SS[0:2] are inputs, forcing the PLL to lock only to a selected data rate . SS2 SS1 SS0 DATA RATE SELECTED/FORCED (Mb/s) 143 177 270 360 540 1483.5/1485 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 27 ASI/177 Logic Input When set HIGH, the device disables the 177Mb/s data rate in the data rate detection circuit. This prevents a false lock to 177Mb/s when using DVB-ASI. When set LOW, 177Mb/s lock is possible, however, if a 270Mb/s ASI signal is applied, the device could false lock to the 177MHz signal. 28 LOCKED Output Lock Detect. This pin is set HIGH by the device when the PLL is locked. 29 LOS Output Loss of Signal. Set HIGH when there are no transitions on the active DDI[3:0] input. See Lock and LOS on page 22. 30 VCC_DIG Power Most positive power supply connection for the internal glue logic. Connect to 3.3V. 31 VEE_DIG Power Most negative power supply connection for the internal glue logic. Connect to GND. 33 SD/HD (GS1575A only) Output This signal will be set LOW by the device when the reclocker has locked to 1.485Gbps or 1.485/1.001Gbps, or when a non-SMPTE standard is applied (i.e. the device is not locked). It will be set HIGH when the reclocker has locked to 143Mbps, 177Mbps, 270Mbps, 360Mbps, or 540Mbps. 33 SD (GS9075A only) Output This signal will go HIGH when the reclocker has locked to the input SD signal. It will be LOW otherwise. Controls the loop bandwidth of the PLL. Leave this pin floating for serial reclocking applications. 34 KBB Analog Input 35 SCO_ENABLE Power Serial clock output enable. Connect to VCC to enable the serial clock output. Connect to GND to disable the serial clock output. NOTE: This is not a TTL signal input. 34716 - 0 December 2005 7 of 29 GS1575A / GS9075A Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 36 38, 40 Name DDO_MUTE SCO, SCO Type Logic Input Output Description Mutes the DDO/DDO outputs. This option is not available in bypass mode. Serial clock output. When SCO_ENABLE is set HIGH, a serial digital differential clock will be presented to the application layer at the selected data rate. 39, 45, 54 - 59 41 NC VCC_SCO No Connect Power Not connected internally. Most positive power supply connection for the SCO/SCO output driver. Connect to 3.3V. 42 VEE_SCO Power Most negative power supply connection for the SCO/SCO output driver. Connect to GND. 43 44, 46 47 GND_DRV DDO, DDO VCC_DDO Passive Output Power Recommended connect to GND. Differential Serial Digital Outputs. Most positive power supply connection for the DDO/DDO output driver. Connect to 3.3V. 48 VEE_DDO Power Most negative power supply connection for the DDO/DDO output driver. Connect to GND. 50, 51 52, 53 60 XTAL_OUT+, XTAL_OUTXTAL+, XTALVEE_CP Output Input Power Differential outputs of the reference oscillator used for monitoring or test purposes. Reference crystal input. Connect to the GO1535 as shown in the Typical Application Circuits on page 24. Most negative power supply connection for the internal charge pump. Connect to GND. 61 VCC_CP Power Most positive power supply connection for the internal charge pump. Connect to 3.3V. 62, 63 - LF+, LFCenter Pad Passive - Loop filter capacitor connection. Connect as shown in the Typical Application Circuits on page 24. Ground pad on bottom of package. Solder to main ground plane following recommendations under Recommended PCB Footprint on page 27. 34716 - 0 December 2005 8 of 29 GS1575A / GS9075A Data Sheet 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Range Input ESD Voltage Solder Reflow Temperature Value +3.6 VDC Vcc + 0.5V 0C to 70C -50C < Ts < 125C 1kV 260C 2.2 DC Electrical Characteristics Table 2-1: DC Electrical Characteristics VCC = 3.3V, TA = 0C to 70C, unless otherwise shown Parameter Supply Voltage Supply Current Symbol VCC ICC ICC Conditions Operating Range SCO enabled, TA=25C SCO disabled, TA=25C SCO enabled, TA=25C SCO disabled, TA=25C High Low Min 3.135 - Typ 3.3 215 Max 3.465 260 Units V mA - 195 230 mA Power Consumption - - 710 - mW - - 645 - mW Logic Inputs DDI_SEL[1:0], BYPASS, AUTOBYPASS, AUTO/MAN, ASI/177, DDO_MUTE Logic Outputs SD/HD, LOCKED, LOS Bi-Directional Pins (Manual Mode) SS[2:0], AUTO/MAN = 0 VIH VIL 2.0 - - - - 0.8 V V VOH VOL VIH VIL 250uA Load 250uA Load High Low 2.8 - 2.0 - - - - - - 0.5 - 0.8 V V V V 34716 - 0 December 2005 9 of 29 GS1575A / GS9075A Data Sheet Table 2-1: DC Electrical Characteristics (Continued) VCC = 3.3V, TA = 0C to 70C, unless otherwise shown Parameter Bi-Directional Pins (Auto Mode) SS[2:0], AUTO/MAN = 1 XTAL_OUT+, XTAL_OUT- Symbol VOH VOL VOH VOL Conditions High, 250uA Load Low, 250uA Load High Low 1.5mA of current delivered Common Mode Min 2.8 - - - VCC - 0.165 1.65 + (VSID/2) - Typ - - VCC VCC - 0.285 - - Max - 0.5 - - VCC + 0.165 VCC (VSID/2) - Units V V V V V V SCO_ENABLE Serial Input Voltage - - Serial Output Voltage SDO/SDO, SCO/SCO - Common Mode VCC - (VOD/2) V 2.3 AC Electrical Characteristics Table 2-2: AC Electrical Characteristics VCC = 3.3V, TA = 0C to 70C, unless otherwise shown Parameter Serial Input Data Rate Symbol - - Conditions GS1575A GS9075A Worst case modulation (e.g. square wave modulation) 143, 270, 360, 1485 Mb/s Min 143 143 0.8 Typ - - - Max 1485 540 - Units Mb/s Mb/s UI Serial Input Jitter Tolerance - PLL Lock Time - Asynchronous PLL Lock Time - Synchronous t ALOCK t SLOCK t SLOCK - CLF=47nF, SD/HD=0 CLF=47nF, SD/HD=1 50 load (on chip) 50 load (on chip) Differential with internal 100 input termination See Figure 2-1 - - - - - 100 - - - 114 106 - 10 10 39 - - 800 ms us us ps ps mVp-p Serial Output Rise/Fall Time SDO/SDO and SCO/SCO (20% - 80%) Serial Digital Input Signal Swing trSDO,trSCO tfSDO,tfSCO VSID Serial Digital Output Signal Swing SDO/SDO and SCO/SCO VOD 100 load differential See Figure 2-2 1400 1600 2200 mVp-p 34716 - 0 December 2005 10 of 29 GS1575A / GS9075A Data Sheet Table 2-2: AC Electrical Characteristics (Continued) VCC = 3.3V, TA = 0C to 70C, unless otherwise shown Parameter Serial Output Jitter SDO/SDO and SCO/SCO KBB = Float PRN, 223-1 Measurement is output jitter that includes input jitter from BERT. Symbol tOJ tOJ tOJ tOJ tOJ tOJ tOJ Conditions 143 Mb/s 177 Mb/s 270 Mb/s 360 Mb/s 540 Mb/s 1485 Mb/s (GS1575A only) Bypass 1.485 Gb/s, KBB = FLOAT (GS1575A only) 1.485 Gb/s, KBB = GND, <0.1dB Peaking (GS1575A only) Min - - - - - - - - - Typ 0.02 0.02 0.02 0.03 0.03 0.06 0.06 1.75 3.2 Max - - 0.09 - 0.09 0.13 0.13 - - Units UI UI UI UI UI UI UI MHz MHz Loop Bandwidth BWLOOP BWLOOP BWLOOP BWLOOP 270 Mb/s, KBB = FLOAT 270 Mb/s, KBB = GND - - 520 1000 - - KHz KHz 34716 - 0 December 2005 11 of 29 GS1575A / GS9075A Data Sheet VCC VCC _ VSID 2 VDD VCC _ VSID 2 + VSID 2 0 _ VSID 2 VSID Differential Swing (DDIx-DDIx) VSID 2 Single-Ended Swing (DDIx) VSID 2 Single-Ended Swing (DDIx) Figure 2-1: Serial Digital Input Signal Swing VCC VCC _ VOD 2 VDD VCC _ VOD 2 + VOD 2 0 _ VOD 2 VOD Differential Swing (DDO-DDO) (SCO-SCO) VOD 2 Single-Ended Swing (DDO, SCO) VOD 2 Single-Ended Swing (DDO, SCO) Figure 2-2: Serial Digital Output Signal Swing 34716 - 0 December 2005 12 of 29 GS1575A / GS9075A Data Sheet 2.4 Solder Reflow Profiles The device is manufactured with Matte-Sn terminations and is compatible with both standard eutectic and Pb-free solder reflow profiles. MSL qualification was performed using the maximum Pb-free reflow profile shown in Figure 2-3. The recommended standard Pb reflow profile is shown in Figure 2-4. Temperature 60-150 sec. 20-40 sec. 260C 250C 3C/sec max 217C 6C/sec max 200C 150C 25C Time 60-180 sec. max 8 min. max Figure 2-3: Maximum Pb-free Solder Reflow Profile (Preferred) Temperature 60-150 sec. 10-20 sec. 230C 220C 3C/sec max 183C 6C/sec max 150C 100C 25C Time 120 sec. max 6 min. max Figure 2-4: Standard Pb Solder Reflow Profile (Pb-free package) 34716 - 0 December 2005 13 of 29 GS1575A / GS9075A Data Sheet 3. Input / Output Circuits VREF Figure 3-1: TTL Inputs LF+ LF- Figure 3-2: Loop Filter 250R 10p 250R 5K 5K XTAL+ XTAL- Figure 3-3: Crystal Input 34716 - 0 December 2005 14 of 29 GS1575A / GS9075A Data Sheet 1K 1K XTAL OUT+ XTAL OUT- Figure 3-4: Crystal Output Buffer 50 SDO/SCO 50 SDO/SCO Figure 3-5: Serial Data Outputs, Serial Clock Outputs V REF KBB 500R Figure 3-6: KBB 34716 - 0 December 2005 15 of 29 GS1575A / GS9075A Data Sheet Figure 3-7: Indicator Outputs: SD/HD, LOCKED, LOS SS[2:0] vREF Figure 3-8: Standard Select/Indication Bi-directional Pins DDI[3:0] 50 1k 1k DDI_VTT 50 DDI[3:0] Figure 3-9: Serial Data Inputs 34716 - 0 December 2005 16 of 29 GS1575A / GS9075A Data Sheet 4. Detailed Description The GS1575A/9075A is a Multi-Rate Serial Digital Reclocker designed to automatically recover the embedded clock from a digital video signal and re-time the incoming video data. The GS1575A will recover the embedded clock signal and re-time the data from a SMPTE 292M, SMPTE 259M or SMPTE 344M compliant digital video signal. The GS9075A will recover the embedded clock signal and re-time the data from a SMPTE 259M or SMPTE 344M compliant digital video signal. Using the functional block diagram (page 2) as a guide, Slew Rate Phase Lock Loop (S-PLL) on page 17 to Output Mute on page 23 describes each aspect of the GS1575A/9075A in detail. 4.1 Slew Rate Phase Lock Loop (S-PLL) The term "slew" refers to the output phase of the PLL in response to a step change at the input. Linear PLLs have an output phase response characterized by an exponential response whereas an S-PLL's output is a ramp response (see Figure 4-1). Because of this non-linear response characteristic, traditional small signal analysis is not possible with an S-PLL. 0.2 PHASE (UI) INPUT 0.1 OUTPUT 0.0 SLEW PLL RESPONSE 0.2 PHASE (UI) INPUT 0.1 OUTPUT 0.0 LINEAR (CONVENTIONAL) PLL RESPONSE Figure 4-1: PLL Characteristics 34716 - 0 December 2005 17 of 29 GS1575A / GS9075A Data Sheet The S-PLL offers several advantages over the linear PLL. The Loop Bandwidth of an S-PLL is independent of the transition density of the input data. Pseudo-random data has a transition density of 0.5 verses a pathological signal which has a transition density of 0.05. The loop bandwidth of a linear PLL will change proportionally with this change in transition density. With an S-PLL, the loop bandwidth is defined by the jitter at the data input. This translates to infinite loop bandwidth with a zero jitter input signal. This allows the loop to correct for small variations in the input jitter quickly, resulting in very low output jitter. The loop bandwidth of the GS1575A/9075A's PLL is defined at 0.2UI of input jitter. The PLL consists of two acquisition loops. First is the Frequency Acquisition (FA) loop. This loop is active when the device is not locked and is used to achieve lock to the supported data rates. Second is the phase acquisition (PA) loop. Once locked, the PA loop tracks the incoming data and makes phased corrections to produce a re-clocked output. 4.2 VCO The internal VCO of the GS1575A/9075A is a ring oscillator. It is trimmed at the time of manufacture to capture all data rates over temperature and operation voltage ranges. Integrated into the VCO is a series of programmable dividers used to achieve all serial data rates, as well as additional dividers for the frequency acquisition loop. 4.3 Charge Pump A common charge pump is used for the PLL of the GS1575A/9075A. During frequency acquisition, the charge pump has two states, "pump-up" and "pump-down," which is produced by a leading or lagging phase difference between the input and the VCO frequency. During phase acquisition, there are two levels of "pump-up" and two levels of "pump down" produced for leading and lagging phase difference between the input and VCO frequency. This is to allow for greater precision of VCO control. The charge pump produces these signals by holding the integrated frequency information on the external loop-filter capacitor, CLF. The instantaneous frequency information is the result of the current flowing through an internal resistor connected to the loop-filter capacitor. 34716 - 0 December 2005 18 of 29 GS1575A / GS9075A Data Sheet 4.4 Frequency Acquisition Loop -- The Phase-Frequency Detector An external crystal of 14.140 MHz is used as a reference to keep the VCO centered at the last known data rate. This allows the device to achieve a fast synchronous lock, especially in cases where a known data rate is interrupted. The crystal reference is also used to clock internal timers and counters. To keep the optimal performance of the reclocker over all operating conditions, the crystal frequency must be 14.140 MHz, +/-50ppm. The GO1535 meets this specification and is available from GENNUM. The VCO is divided by a selected ratio which is dependant on the input data rate. The resultant is then compared to the crystal frequency. If the divided VCO frequency and the crystal frequency are within 1% of each other, the PLL is considered to be locked to the input data rate. 4.5 Phase Acquisition Loop -- The Phase Detector The phase detector is a digital quadrature phase detector. It indicates whether the input data is leading or lagging with respect to a clock that is in phase with the VCO (I-clk) and a quadrature clock (Q-clk). When the phase acquisition loop (PA loop) is locked, the input data transition is aligned to the falling edge of I-clk and the output data is re-timed on the rising edge of I-clk. During high input jitter conditions (>0.25UI), Q-clk will sample a different value than I-clk. In this condition, two extra phase correction signals will be generated which instructs the charge pump to create larger frequency corrections for the VCO. i-PHASE ALIGNMENT EDGE DATA RE-TIMING EDGE I-clk q-clk q-PHASE ALIGNMENT EDGE INPUT DATA WITH JITTER 0.25UI 0.8UI RE-TIMED OUTPUT DATA Figure 4-2: Phase Detector Characteristics When the PA loop is active, the crystal frequency and the incoming data rate are compared. If the resultant is more that 2%, the PLL is considered to be unlocked and the system jumps to the FA loop. 34716 - 0 December 2005 19 of 29 GS1575A / GS9075A Data Sheet 4.6 4:1 Input Mux The 4:1 input mux allows the connection of four independent streams of video/data. There are four differential inputs (DDI[3:0] and DDI[3:0]). The active channel can be selected via the DDI_SEL[1:0] pins. Table 4-1 shows the input selected for a given state at DDI_SEL[1:0]. Table 4-1: Bit Pattern for Input Select DDI_SEL[1:0] 00 01 10 11 Selected Input DDI0 DDI1 DDI2 DDI3 The DDI inputs are designed to be DC interfaced with the output of the GS1524A/9064A Cable Equalizer. There are on chip 50 termination resistors which come to a common point at the DDI_VT pins. Connect a 10nF capacitor to this pin and connect the other end of the capacitor to ground. This terminates the transmission line at the inputs for optimum performance. If only one input pair is used, connect the unused positive inputs to +3.3V and leave the unused negative inputs floating. This helps to eliminate crosstalk from potential noise that would couple to the unused input pair. 4.7 Automatic and Manual Data Rate Selection The GS1575A/9075A can be configured to manually lock to a specific data rate or automatically search for and lock to the incoming data rate. The AUTO/MAN pin selects automatic data rate detection mode (Auto mode) when HIGH and manual data rate selection mode (Manual mode) when LOW. In Auto mode, the SS[2:0] bi-directional pins become outputs and the bit pattern indicates the data rate that the PLL is locked to (or previously locked to). The "search algorithm" cycles through the data rates and starts over if that data rate is not found (see Figure 4-3). POWER-UP 143 Mb\s 177 Mb\s 270Mb\s 360 Mb\s 1.485Mb\s (GS1575A only) 540 Mb\s Figure 4-3: Data Rate Search Pattern 34716 - 0 December 2005 20 of 29 GS1575A / GS9075A Data Sheet In Manual mode, the SS[2:0] pins become inputs and the data rate can be programmed by the application layer. In this mode, the search algorithm is disabled and the PLL will only lock to the data rate selected. Table 4-2 shows the SS[2:0] pin settings for either the data rate selected (in Manual mode) or the data rate that the PLL has locked to (in Auto mode). Table 4-2: Data Rate Indication/Selection Bit Pattern SS[2:0] 000 001 010 011 100 101* Data Rate (Mb/s) 143 177 270 360 540 1485/1483.5 * This setting only applies to the GS1575A. For the GS9075A, when AUTO/MAN is LOW, the pin settings SS[0:2] = 101 will be ignored by the device. 4.8 Bypass Mode In Bypass mode, the GS1575A/9075A passes the data at the inputs directly to the outputs. There are two pins that control the bypass function: BYPASS and AUTOBYPASS. When BYPASS is set HIGH by the application layer, the GS1575A/9075A will be in Bypass mode. When AUTOBYPASS is set HIGH by the application layer, the GS1575A/9075A will be configured to enter Bypass mode only when the PLL has not locked to a data rate. When BYPASS is set HIGH, AUTOBYPASS will be ignored. When the PLL is not locked, and both BYPASS and AUTOBYPASS are set LOW, the serial digital output DDO/DDO will produce invalid data. 4.9 DVB-ASI Operation The GS1575A/9075A will also re-clock DVB-ASI at 270 Mb/s. When reclocking DVB-ASI data set the ASI/177 pin HIGH to prevent a false lock to 177Mb/s. If ASI/177 is not set HIGH, a false lock may occur since there is a harmonic present in idle patterns (K28.5) which is very close the 177 Mb/s data rate (EIC 1179). Note that setting the ASI/177 pin HIGH will disable the 177 Mb/s search when the device is in Auto mode, consequently the GS1575A/9075A will not lock to that data rate. 34716 - 0 December 2005 21 of 29 GS1575A / GS9075A Data Sheet 4.10 Lock and LOS The LOCKED signal is an active high output which indicates when the PLL is locked. The internal lock logic of the GS1575A/9075A includes a system which monitors the Frequency Acquisition Loop and the Phase Acquisition Loop as well as a monitor to detect harmonic lock. The LOS (Loss of Signal) output is an active HIGH output which indicates the absence of data transitions at the DDIx input. In order for this output to be asserted, transitions must not be present for a period of typically 5.14 us. After this output has been asserted, LOS will deassert typically 5.14 us after the appearance of a transition at the DDIx input. This timing relationship is shown in Figure 4-4: 5.14 us 5.14 us DATA LOS Figure 4-4: LOS signal timing NOTE: LOS is sensitive to transitions appearing at the input, and does not distinguish between transitions caused by input data, and transitions due to noise. 4.11 Output Drivers and Serial Clock Outputs The device's serial digital data outputs (DDO/DDO) have a nominal voltage of 800mv single ended or 1600mV differential when terminated into a 50 load. The GS1575A/9075A may also be configured to output a serial clock at the data output rate. The internal serial clock output block is powered via the SCO_ENABLE pin. When SCO_ENABLE is connected to VCC, a differential serial clock output will be present on SCO/SCO. Otherwise, when SCO_ENABLE is connected to GND, the clock output block will be powered down and the device will have reduced power consumption. NOTE: The SCO_ENABLE signal should have a 1.5mA drive strength to maintain a supply voltage of 3.3 +/- 0.165V. Clock and data alignment is shown in Figure 4-5. 34716 - 0 December 2005 22 of 29 GS1575A / GS9075A Data Sheet DATA SCLK For HD-SDI: tCD = 32ps (typ.), 36ps (max.) For SD-SDI: tCD = 30ps (typ.), 38ps (max.) tCD Figure 4-5: Clock and Data Alignment 4.12 Output Mute The DDO_MUTE pin is provided to allow muting of the re-timed output. When the PLL is locked and the device is reclocking, setting DDO_MUTE = LOW will force the serial digital outputs DDO/DDO to mute. However, if the GS1575A/9075A is in Bypass mode, (AUTOBYPASS = HIGH and/or BYPASS = HIGH), DDO_MUTE will have no effect on the output. 34716 - 0 December 2005 23 of 29 GS1575A / GS9075A Data Sheet 5. Typical Application Circuits GO1535 (14.140MHz) 47n 3.3V 100 10n 55 GND 64 63 62 61 60 59 58 57 56 54 53 XT AL + 5 2 51 XT AL _ O U T 50 XT AL _ O U T + VC C _ C P XT AL - VEE_ C P GND NC LF+ NC NC LF- NC NC NC 49 1 DDI0 DDI0_VT DDI0 GN D DDI1 DDI1_VT DDI1 GN D DDI2 DDI2_VT DDI2 GN D DDI3 DDI3_VT DDI3 AUTOBYPASS AUTO/MAN GN D DDI_SEL0 DDI_SEL1 BYPASS VCC_VCO VEE_DDO VCC_DDO DDO NC DDO GND VEE_SCO 48 1 0n 47 46 45 44 43 42 1 0n 41 40 3.3V 3.3V D A TA I N PU T 0 Zo = 50 2 10n 3 4 5 Zo = 50 DATA OUTPUT D A TA I N PU T 1 Zo = 50 6 10n 7 8 9 GS1575A VCC_SCO SCO NC SCO GND DDO_MUTE SCO_ENABLE KBB SD/HD VCC_DIG 33 SD /H D 39 38 37 36 35 34 SD O _ MU T E D ATA I N PU T 2 Zo = 50 10 10n 11 12 13 Zo = 50 CLOCK OUTPUT D A TA I N PU T 3 Zo = 50 14 10n 15 16 VEE_VC0 VEE_DIG 31 3.3V LOCKED ASI/177 17 18 19 20 21 22 23 24 25 26 27 28 29 30 10n DDI_SEL0 DDI_SEL1 ASI_177 3.3V 10n 32 GND LOS SS0 SS1 SS2 LOS LOCKED Note: All resistors in ohms and all capacitors in Farads. Figure 5-1: GS1575A Typical Application Circuit 34716 - 0 December 2005 24 of 29 GS1575A / GS9075A Data Sheet G O 1535 (14.140MHz ) 47n 3.3V 100 10n 55 G ND 64 63 62 61 60 59 58 57 56 54 53 X TAL+ 52 51 X TAL_O UT50 X TAL_O UT+ V CC_CP X TAL- V E E _CP G ND NC LF+ NC NC LF- NC NC NC 49 1 DDI0 DDI0_V T DDI0 GND DDI1 DDI1_V T DDI1 GND DDI2 DDI2_V T DDI2 GND DDI3 DDI3_V T DDI3 AUTO BYPASS AUTO /MAN GND DDI_ SEL0 DDI_ SEL1 BYPASS VCC_ VCO VEE_ DDO VCC_ DDO DDO NC DDO G ND VEE_ SCO 48 10n 47 46 45 44 43 42 10n 41 40 3.3V 3.3V DATA INPUT 0 Zo = 50 2 10n 3 4 5 Zo = 5 0 DA TA OUTPUT DATA INPUT 1 Z o = 50 6 10n 7 8 9 GS 9075A VCC_ SCO SCO NC SCO G ND DDO _ MUTE SCO _ ENABLE KBB SD VCC_ DIG 33 SD 39 38 37 36 35 34 SDO_MUTE DATA INPUT 2 Zo = 50 10 10n 11 12 13 Zo = 5 0 C LOCK OUTPUT DATA INPUT 3 Zo = 50 14 10n 15 16 VEE_ VC0 VEE_ DIG 31 3.3V LO CKED ASI/177 17 18 19 20 21 22 23 24 25 26 27 28 29 30 10n DDI_S E L0 DDI_S E L1 A S I_177 3.3V 10n 32 G ND LO S SS0 SS1 SS2 LO S LO CKED Note: All resistors in ohms and all capacitors in Farads. Figure 5-2: GS9075A Typical Application Circuit 34716 - 0 December 2005 25 of 29 GS1575A / GS9075A Data Sheet 6. Package & Ordering Information 6.1 Package Dimensions 0.40+/-0.05 0.95+/-0.05 3.55 45 9.00 4.50 A B 7.10+/-0.15 4.50 0.35 9.00 PIN 1 AREA CENTRE TAB 2X 0.15 C 4.50 2X 0.10 C 0.15 C 0.20 REF +0.03 0.25-0.02 0.50 64X C CAB 0.10 C 0.05 64X 0.08 C 0.90 +/- 0.10 +0.03 0.02-0.02 SEATING PLANE ALL DIMENSIONS IN MM 34716 - 0 December 2005 26 of 29 3.55 7.10+/-0.15 GS1575A / GS9075A Data Sheet 6.2 Recommended PCB Footprint 0.50 0.25 0.55 CENTER PAD 8.70 7.10 7.10 8.70 NOTE: All dimensions are in millimeters. The center pad of the PCB footprint should be connected to the ground plane by a minimum of 36 vias. NOTE: Suggested dimensions only. Final dimensions should conform to customer design rules and process optimizations. 34716 - 0 December 2005 27 of 29 GS1575A / GS9075A Data Sheet 6.3 Packaging Data Parameter Package Type Moisture Sensitivity Level Junction to Case Thermal Resistance, j-c Junction to Air Thermal Resistance, j-a (at zero airflow) Psi, Pb-free and RoHS Compliant Value 9mm x 9mm 64-pin QFN 3 9.1C/W 21.5C/W 0.2C/W Yes 6.4 Ordering Information Part Number GS1575A GS9075A GS1575ACNE3 GS9075ACNE3 Package Pb-free 64-pin QFN Pb-free 64-pin QFN Temperature Range 0C to 70C 0C to 70C 34716 - 0 December 2005 28 of 29 GS1575A / GS9075A Data Sheet 7. Revision History Version A 0 ECR 136456 137416 PCN - - Date April 2005 December 2005 Changes and/or Modifications New Document. Converted to Data Sheet. Added block diagram, pinout, DC and AC electrical, and circuit information for serial clock output support. Added information on GS9075A. Added LOS support information. Corrected minor typing errors. Corrected maximum Serial Digital Output swing to 2200 mV. Corrected packaging diagram. CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION DATA SHEET The product is in production. Gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. GENNUM CORPORATION Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. GENNUM and the G logo are registered trademarks of Gennum Corporation. (c) Copyright 2005 Gennum Corporation. All rights reserved. Printed in Canada. www.gennum.com 34716 - 0 December 2005 29 29 of 29 |
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